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[shader_recompiler] simplify decoder table logic and let compiler do tables for us (#2915) 

The compiler is very smart, I trust the compiler to make a proper decoder selector rather than rolling our own.

Probably mostly benefitted on PGO builds.

Directly affects cache recompilation times (test with pipeline shaders OFF to force shaders to rebuild :)

Also restores CCTLT so we have the full ISA (or do we? Is ISBEWR missing? - someone should run fuzzing :)

Signed-off-by: lizzie <lizzie@eden-emu.dev>
Reviewed-on: https://git.eden-emu.dev/eden-emu/eden/pulls/2915
Reviewed-by: MaranBr <maranbr@eden-emu.dev>
Co-authored-by: lizzie <lizzie@eden-emu.dev>
Co-committed-by: lizzie <lizzie@eden-emu.dev>
This commit is contained in:
lizzie 2025-11-01 03:57:28 +01:00 committed by crueter
parent ea6c3c379c
commit fe6b6fbde5
No known key found for this signature in database
GPG Key ID: 425ACD2D4830EBC6
4 changed files with 222 additions and 313 deletions
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131
src/shader_recompiler/frontend/maxwell/decode.cpp
View File

@ -7,142 +7,45 @@
#include <array>
#include <bit>
#include <memory>
#include <ranges>
#include <string_view>
#include "common/common_types.h"
#include <ranges>
#include "shader_recompiler/exception.h"
#include "shader_recompiler/frontend/maxwell/decode.h"
#include "shader_recompiler/frontend/maxwell/opcodes.h"
namespace Shader::Maxwell {
namespace {
struct MaskValue {
u64 mask;
u64 value;
};
constexpr MaskValue MaskValueFromEncoding(const char* encoding) {
u64 mask{};
u64 value{};
u64 bit{u64(1) << 63};
while (*encoding) {
switch (*encoding) {
consteval std::pair<u64, u64> MaskValueFromEncoding(const char data[20]) noexcept {
u64 mask = 0, value = 0, bit = u64(1) << 63;
for (int i = 0; i < 20; ++i)
switch (data[i]) {
case '0':
mask |= bit;
bit >>= 1;
break;
case '1':
mask |= bit;
value |= bit;
bit >>= 1;
break;
case '-':
break;
case ' ':
bit >>= 1;
break;
default:
throw LogicError("Invalid encoding character '{}'", *encoding);
break;
}
++encoding;
if (*encoding != ' ') {
bit >>= 1;
return { mask, value };
}
}
return MaskValue{.mask = mask, .value = value};
}
struct InstEncoding {
MaskValue mask_value;
Opcode opcode;
};
constexpr auto SortedEncodings() {
std::array<InstEncoding, 279> encodings{
#define INST(name, cute, encode) \
InstEncoding{ \
.mask_value{MaskValueFromEncoding(encode)}, \
.opcode = Opcode::name, \
},
#include "maxwell.inc"
#undef INST
};
std::ranges::sort(encodings, [](const InstEncoding& lhs, const InstEncoding& rhs) {
return std::popcount(lhs.mask_value.mask) > std::popcount(rhs.mask_value.mask);
});
return encodings;
}
constexpr auto ENCODINGS{SortedEncodings()};
constexpr int WidestLeftBits() {
int bits{64};
for (const InstEncoding& encoding : ENCODINGS) {
bits = (std::min)(bits, std::countr_zero(encoding.mask_value.mask));
}
return 64 - bits;
}
constexpr int WIDEST_LEFT_BITS{WidestLeftBits()};
constexpr int MASK_SHIFT{64 - WIDEST_LEFT_BITS};
constexpr size_t ToFastLookupIndex(u64 value) {
return static_cast<size_t>(value >> MASK_SHIFT);
}
constexpr size_t FastLookupSize() {
size_t max_width{};
for (const InstEncoding& encoding : ENCODINGS) {
max_width = (std::max)(max_width, ToFastLookupIndex(encoding.mask_value.mask));
}
return max_width + 1;
}
constexpr size_t FAST_LOOKUP_SIZE{FastLookupSize()};
struct InstInfo {
[[nodiscard]] u64 Mask() const noexcept {
return static_cast<u64>(high_mask) << MASK_SHIFT;
}
[[nodiscard]] u64 Value() const noexcept {
return static_cast<u64>(high_value) << MASK_SHIFT;
}
u16 high_mask;
u16 high_value;
Opcode opcode;
};
constexpr auto MakeFastLookupTableIndex(size_t index) {
std::array<InstInfo, 2> encodings{};
size_t element{};
for (const auto& encoding : ENCODINGS) {
const size_t mask{ToFastLookupIndex(encoding.mask_value.mask)};
const size_t value{ToFastLookupIndex(encoding.mask_value.value)};
if ((index & mask) == value) {
encodings.at(element) = InstInfo{
.high_mask = static_cast<u16>(encoding.mask_value.mask >> MASK_SHIFT),
.high_value = static_cast<u16>(encoding.mask_value.value >> MASK_SHIFT),
.opcode = encoding.opcode,
};
++element;
}
}
return encodings;
}
/*constexpr*/ auto MakeFastLookupTable() {
auto encodings{std::make_unique<std::array<std::array<InstInfo, 2>, FAST_LOOKUP_SIZE>>()};
for (size_t index = 0; index < FAST_LOOKUP_SIZE; ++index) {
(*encodings)[index] = MakeFastLookupTableIndex(index);
}
return encodings;
}
const auto FAST_LOOKUP_TABLE{MakeFastLookupTable()};
} // Anonymous namespace
Opcode Decode(u64 insn) {
const auto& table{(*FAST_LOOKUP_TABLE)[ToFastLookupIndex(insn)]};
const auto it{std::ranges::find_if(
table, [insn](const InstInfo& info) { return (insn & info.Mask()) == info.Value(); })};
if (it == table.end()) {
throw NotImplementedException("Instruction 0x{:016x} is unknown / unimplemented", insn);
}
return it->opcode;
#define INST(name, cute, encode) \
if (auto const p = MaskValueFromEncoding(encode); (insn & p.first) == p.second) \
return Opcode::name;
#include "maxwell.inc"
#undef INST
throw NotImplementedException("Invalid insn 0x{:016x}", insn);
}
} // namespace Shader::Maxwell

396
src/shader_recompiler/frontend/maxwell/maxwell.inc
View File

@ -1,285 +1,283 @@
// SPDX-FileCopyrightText: Copyright 2021 yuzu Emulator Project
// SPDX-License-Identifier: GPL-2.0-or-later
INST(CCTLT, "CCTLT", "1110 1011 1111 0--0")
INST(AL2P, "AL2P", "1110 1111 1010 0---")
INST(ALD, "ALD", "1110 1111 1101 1---")
INST(AST, "AST", "1110 1111 1111 0---")
INST(ATOM_cas, "ATOM (cas)", "1110 1110 1111 ----")
INST(ATOM, "ATOM", "1110 1101 ---- ----")
INST(ATOMS_cas, "ATOMS (cas)", "1110 1110 ---- ----")
INST(ATOMS, "ATOMS", "1110 1100 ---- ----")
INST(B2R, "B2R", "1111 0000 1011 1---")
INST(BAR, "BAR", "1111 0000 1010 1---")
INST(BFE_reg, "BFE (reg)", "0101 1100 0000 0---")
INST(BFE_cbuf, "BFE (cbuf)", "0100 1100 0000 0---")
INST(BFE_imm, "BFE (imm)", "0011 100- 0000 0---")
INST(BFI_reg, "BFI (reg)", "0101 1011 1111 0---")
INST(BFI_rc, "BFI (rc)", "0101 0011 1111 0---")
INST(BFE_reg, "BFE (reg)", "0101 1100 0000 0---")
INST(BFI_cr, "BFI (cr)", "0100 1011 1111 0---")
INST(BFI_rc, "BFI (rc)", "0101 0011 1111 0---")
INST(BFI_reg, "BFI (reg)", "0101 1011 1111 0---")
INST(CS2R, "CS2R", "0101 0000 1100 1---")
INST(CSET, "CSET", "0101 0000 1001 1---")
INST(CSETP, "CSETP", "0101 0000 1010 0---")
INST(DADD_cbuf, "DADD (cbuf)", "0100 1100 0111 0---")
INST(DADD_reg, "DADD (reg)", "0101 1100 0111 0---")
INST(DEPBAR, "DEPBAR", "1111 0000 1111 0---")
INST(DMNMX_cbuf, "DMNMX (cbuf)", "0100 1100 0101 0---")
INST(DMNMX_reg, "DMNMX (reg)", "0101 1100 0101 0---")
INST(DMUL_cbuf, "DMUL (cbuf)", "0100 1100 1000 0---")
INST(DMUL_reg, "DMUL (reg)", "0101 1100 1000 0---")
INST(F2F_cbuf, "F2F (cbuf)", "0100 1100 1010 1---")
INST(F2F_reg, "F2F (reg)", "0101 1100 1010 1---")
INST(F2I_cbuf, "F2I (cbuf)", "0100 1100 1011 0---")
INST(F2I_reg, "F2I (reg)", "0101 1100 1011 0---")
INST(FADD_cbuf, "FADD (cbuf)", "0100 1100 0101 1---")
INST(FADD_reg, "FADD (reg)", "0101 1100 0101 1---")
INST(FCHK_cbuf, "FCHK (cbuf)", "0100 1100 1000 1---")
INST(FCHK_reg, "FCHK (reg)", "0101 1100 1000 1---")
INST(FLO_cbuf, "FLO (cbuf)", "0100 1100 0011 0---")
INST(FLO_reg, "FLO (reg)", "0101 1100 0011 0---")
INST(FMNMX_cbuf, "FMNMX (cbuf)", "0100 1100 0110 0---")
INST(FMNMX_reg, "FMNMX (reg)", "0101 1100 0110 0---")
INST(FMUL_cbuf, "FMUL (cbuf)", "0100 1100 0110 1---")
INST(FMUL_reg, "FMUL (reg)", "0101 1100 0110 1---")
INST(FSWZADD, "FSWZADD", "0101 0000 1111 1---")
INST(HADD2_reg, "HADD2 (reg)", "0101 1101 0001 0---")
INST(HFMA2_reg, "HFMA2 (reg)", "0101 1101 0000 0---")
INST(HMUL2_reg, "HMUL2 (reg)", "0101 1101 0000 1---")
INST(HSET2_reg, "HSET2 (reg)", "0101 1101 0001 1---")
INST(HSETP2_reg, "HSETP2 (reg)", "0101 1101 0010 0---")
INST(I2F_cbuf, "I2F (cbuf)", "0100 1100 1011 1---")
INST(I2F_reg, "I2F (reg)", "0101 1100 1011 1---")
INST(I2I_cbuf, "I2I (cbuf)", "0100 1100 1110 0---")
INST(I2I_reg, "I2I (reg)", "0101 1100 1110 0---")
INST(IADD_cbuf, "IADD (cbuf)", "0100 1100 0001 0---")
INST(IADD_reg, "IADD (reg)", "0101 1100 0001 0---")
INST(IDP_imm, "IDP (imm)", "0101 0011 1101 1---")
INST(IDP_reg, "IDP (reg)", "0101 0011 1111 1---")
INST(IMNMX_cbuf, "IMNMX (cbuf)", "0100 1100 0010 0---")
INST(IMNMX_reg, "IMNMX (reg)", "0101 1100 0010 0---")
INST(IMUL_cbuf, "IMUL (cbuf)", "0100 1100 0011 1---")
INST(IMUL_reg, "IMUL (reg)", "0101 1100 0011 1---")
INST(ISBERD, "ISBERD", "1110 1111 1101 0---")
INST(ISCADD_cbuf, "ISCADD (cbuf)", "0100 1100 0001 1---")
INST(ISCADD_reg, "ISCADD (reg)", "0101 1100 0001 1---")
INST(LDC, "LDC", "1110 1111 1001 0---")
INST(LDG, "LDG", "1110 1110 1101 0---")
INST(LDL, "LDL", "1110 1111 0100 0---")
INST(LDS, "LDS", "1110 1111 0100 1---")
INST(LEA_hi_reg, "LEA (hi reg)", "0101 1011 1101 1---")
INST(LEA_lo_reg, "LEA (lo reg)", "0101 1011 1101 0---")
INST(LEPC, "LEPC", "0101 0000 1101 0---")
INST(LOP3_reg, "LOP3 (reg)", "0101 1011 1110 0---")
INST(LOP_cbuf, "LOP (cbuf)", "0100 1100 0100 0---")
INST(LOP_reg, "LOP (reg)", "0101 1100 0100 0---")
INST(MEMBAR, "MEMBAR", "1110 1111 1001 1---")
INST(MOV_cbuf, "MOV (cbuf)", "0100 1100 1001 1---")
INST(MOV_reg, "MOV (reg)", "0101 1100 1001 1---")
INST(MUFU, "MUFU", "0101 0000 1000 0---")
INST(NOP, "NOP", "0101 0000 1011 0---")
INST(OUT_cbuf, "OUT (cbuf)", "1110 1011 1110 0---")
INST(OUT_reg, "OUT (reg)", "1111 1011 1110 0---")
INST(P2R_cbuf, "P2R (cbuf)", "0100 1100 1110 1---")
INST(P2R_imm, "P2R (imm)", "0011 1000 1110 1---")
INST(P2R_reg, "P2R (reg)", "0101 1100 1110 1---")
INST(PIXLD, "PIXLD", "1110 1111 1110 1---")
INST(POPC_cbuf, "POPC (cbuf)", "0100 1100 0000 1---")
INST(POPC_reg, "POPC (reg)", "0101 1100 0000 1---")
INST(PSET, "PSET", "0101 0000 1000 1---")
INST(PSETP, "PSETP", "0101 0000 1001 0---")
INST(R2B, "R2B", "1111 0000 1100 0---")
INST(R2P_cbuf, "R2P (cbuf)", "0100 1100 1111 0---")
INST(R2P_reg, "R2P (reg)", "0101 1100 1111 0---")
INST(RED, "RED", "1110 1011 1111 1---")
INST(RRO_cbuf, "RRO (cbuf)", "0100 1100 1001 0---")
INST(RRO_reg, "RRO (reg)", "0101 1100 1001 0---")
INST(S2R, "S2R", "1111 0000 1100 1---")
INST(SEL_cbuf, "SEL (cbuf)", "0100 1100 1010 0---")
INST(SEL_reg, "SEL (reg)", "0101 1100 1010 0---")
INST(SHFL, "SHFL", "1110 1111 0001 0---")
INST(SHF_l_reg, "SHF (l reg)", "0101 1011 1111 1---")
INST(SHF_r_reg, "SHF (r reg)", "0101 1100 1111 1---")
INST(SHL_cbuf, "SHL (cbuf)", "0100 1100 0100 1---")
INST(SHL_reg, "SHL (reg)", "0101 1100 0100 1---")
INST(SHR_cbuf, "SHR (cbuf)", "0100 1100 0010 1---")
INST(SHR_reg, "SHR (reg)", "0101 1100 0010 1---")
INST(STG, "STG", "1110 1110 1101 1---")
INST(STL, "STL", "1110 1111 0101 0---")
INST(STP, "STP", "1110 1110 1010 0---")
INST(STS, "STS", "1110 1111 0101 1---")
INST(SYNC, "SYNC", "1111 0000 1111 1---")
INST(TMML, "TMML", "1101 1111 0101 1---")
INST(TMML_b, "TMML (b)", "1101 1111 0110 0---")
INST(TXA, "TXA", "1101 1111 0100 0---")
INST(TXQ, "TXQ", "1101 1111 0100 1---")
INST(TXQ_b, "TXQ (b)", "1101 1111 0101 0---")
INST(VOTE, "VOTE", "0101 0000 1101 1---")
INST(VOTE_vtg, "VOTE (vtg)", "0101 0000 1110 0---")
INST(VSETP, "VSETP", "0101 0000 1111 0---")
INST(ATOM_cas, "ATOM (cas)", "1110 1110 1111 ----")
INST(BFE_imm, "BFE (imm)", "0011 100- 0000 0---")
INST(BFI_imm, "BFI (imm)", "0011 011- 1111 0---")
INST(BPT, "BPT", "1110 0011 1010 ----")
INST(BRA, "BRA", "1110 0010 0100 ----")
INST(BRK, "BRK", "1110 0011 0100 ----")
INST(BRX, "BRX", "1110 0010 0101 ----")
INST(CAL, "CAL", "1110 0010 0110 ----")
INST(CCTL, "CCTL", "1110 1111 011- ----")
INST(CCTLL, "CCTLL", "1110 1111 100- ----")
INST(CONT, "CONT", "1110 0011 0101 ----")
INST(CS2R, "CS2R", "0101 0000 1100 1---")
INST(CSET, "CSET", "0101 0000 1001 1---")
INST(CSETP, "CSETP", "0101 0000 1010 0---")
INST(DADD_reg, "DADD (reg)", "0101 1100 0111 0---")
INST(DADD_cbuf, "DADD (cbuf)", "0100 1100 0111 0---")
INST(DADD_imm, "DADD (imm)", "0011 100- 0111 0---")
INST(DEPBAR, "DEPBAR", "1111 0000 1111 0---")
INST(DFMA_reg, "DFMA (reg)", "0101 1011 0111 ----")
INST(DFMA_rc, "DFMA (rc)", "0101 0011 0111 ----")
INST(DFMA_cr, "DFMA (cr)", "0100 1011 0111 ----")
INST(DFMA_imm, "DFMA (imm)", "0011 011- 0111 ----")
INST(DMNMX_reg, "DMNMX (reg)", "0101 1100 0101 0---")
INST(DMNMX_cbuf, "DMNMX (cbuf)", "0100 1100 0101 0---")
INST(DFMA_rc, "DFMA (rc)", "0101 0011 0111 ----")
INST(DFMA_reg, "DFMA (reg)", "0101 1011 0111 ----")
INST(DMNMX_imm, "DMNMX (imm)", "0011 100- 0101 0---")
INST(DMUL_reg, "DMUL (reg)", "0101 1100 1000 0---")
INST(DMUL_cbuf, "DMUL (cbuf)", "0100 1100 1000 0---")
INST(DMUL_imm, "DMUL (imm)", "0011 100- 1000 0---")
INST(DSET_reg, "DSET (reg)", "0101 1001 0--- ----")
INST(DSET_cbuf, "DSET (cbuf)", "0100 1001 0--- ----")
INST(DSET_imm, "DSET (imm)", "0011 001- 0--- ----")
INST(DSETP_reg, "DSETP (reg)", "0101 1011 1000 ----")
INST(DSETP_cbuf, "DSETP (cbuf)", "0100 1011 1000 ----")
INST(DSETP_imm, "DSETP (imm)", "0011 011- 1000 ----")
INST(DSETP_reg, "DSETP (reg)", "0101 1011 1000 ----")
INST(EXIT, "EXIT", "1110 0011 0000 ----")
INST(F2F_reg, "F2F (reg)", "0101 1100 1010 1---")
INST(F2F_cbuf, "F2F (cbuf)", "0100 1100 1010 1---")
INST(F2F_imm, "F2F (imm)", "0011 100- 1010 1---")
INST(F2I_reg, "F2I (reg)", "0101 1100 1011 0---")
INST(F2I_cbuf, "F2I (cbuf)", "0100 1100 1011 0---")
INST(F2I_imm, "F2I (imm)", "0011 100- 1011 0---")
INST(FADD_reg, "FADD (reg)", "0101 1100 0101 1---")
INST(FADD_cbuf, "FADD (cbuf)", "0100 1100 0101 1---")
INST(FADD_imm, "FADD (imm)", "0011 100- 0101 1---")
INST(FADD32I, "FADD32I", "0000 10-- ---- ----")
INST(FCHK_reg, "FCHK (reg)", "0101 1100 1000 1---")
INST(FCHK_cbuf, "FCHK (cbuf)", "0100 1100 1000 1---")
INST(FCHK_imm, "FCHK (imm)", "0011 100- 1000 1---")
INST(FCMP_reg, "FCMP (reg)", "0101 1011 1010 ----")
INST(FCMP_rc, "FCMP (rc)", "0101 0011 1010 ----")
INST(FCMP_cr, "FCMP (cr)", "0100 1011 1010 ----")
INST(FCMP_imm, "FCMP (imm)", "0011 011- 1010 ----")
INST(FFMA_reg, "FFMA (reg)", "0101 1001 1--- ----")
INST(FFMA_rc, "FFMA (rc)", "0101 0001 1--- ----")
INST(FFMA_cr, "FFMA (cr)", "0100 1001 1--- ----")
INST(FFMA_imm, "FFMA (imm)", "0011 001- 1--- ----")
INST(FFMA32I, "FFMA32I", "0000 11-- ---- ----")
INST(FLO_reg, "FLO (reg)", "0101 1100 0011 0---")
INST(FLO_cbuf, "FLO (cbuf)", "0100 1100 0011 0---")
INST(FCMP_rc, "FCMP (rc)", "0101 0011 1010 ----")
INST(FCMP_reg, "FCMP (reg)", "0101 1011 1010 ----")
INST(FLO_imm, "FLO (imm)", "0011 100- 0011 0---")
INST(FMNMX_reg, "FMNMX (reg)", "0101 1100 0110 0---")
INST(FMNMX_cbuf, "FMNMX (cbuf)", "0100 1100 0110 0---")
INST(FMNMX_imm, "FMNMX (imm)", "0011 100- 0110 0---")
INST(FMUL_reg, "FMUL (reg)", "0101 1100 0110 1---")
INST(FMUL_cbuf, "FMUL (cbuf)", "0100 1100 0110 1---")
INST(FMUL_imm, "FMUL (imm)", "0011 100- 0110 1---")
INST(FMUL32I, "FMUL32I", "0001 1110 ---- ----")
INST(FSET_reg, "FSET (reg)", "0101 1000 ---- ----")
INST(FSET_cbuf, "FSET (cbuf)", "0100 1000 ---- ----")
INST(FSET_imm, "FSET (imm)", "0011 000- ---- ----")
INST(FSETP_reg, "FSETP (reg)", "0101 1011 1011 ----")
INST(FSETP_cbuf, "FSETP (cbuf)", "0100 1011 1011 ----")
INST(FSETP_imm, "FSETP (imm)", "0011 011- 1011 ----")
INST(FSWZADD, "FSWZADD", "0101 0000 1111 1---")
INST(FSETP_reg, "FSETP (reg)", "0101 1011 1011 ----")
INST(GETCRSPTR, "GETCRSPTR", "1110 0010 1100 ----")
INST(GETLMEMBASE, "GETLMEMBASE", "1110 0010 1101 ----")
INST(HADD2_reg, "HADD2 (reg)", "0101 1101 0001 0---")
INST(HADD2_cbuf, "HADD2 (cbuf)", "0111 101- 1--- ----")
INST(HADD2_imm, "HADD2 (imm)", "0111 101- 0--- ----")
INST(HADD2_32I, "HADD2_32I", "0010 110- ---- ----")
INST(HFMA2_reg, "HFMA2 (reg)", "0101 1101 0000 0---")
INST(HFMA2_rc, "HFMA2 (rc)", "0110 0--- 1--- ----")
INST(HFMA2_cr, "HFMA2 (cr)", "0111 0--- 1--- ----")
INST(HFMA2_imm, "HFMA2 (imm)", "0111 0--- 0--- ----")
INST(HFMA2_32I, "HFMA2_32I", "0010 100- ---- ----")
INST(HMUL2_reg, "HMUL2 (reg)", "0101 1101 0000 1---")
INST(HMUL2_cbuf, "HMUL2 (cbuf)", "0111 100- 1--- ----")
INST(HMUL2_imm, "HMUL2 (imm)", "0111 100- 0--- ----")
INST(HMUL2_32I, "HMUL2_32I", "0010 101- ---- ----")
INST(HSET2_reg, "HSET2 (reg)", "0101 1101 0001 1---")
INST(HSET2_cbuf, "HSET2 (cbuf)", "0111 110- 1--- ----")
INST(HSET2_imm, "HSET2 (imm)", "0111 110- 0--- ----")
INST(HSETP2_reg, "HSETP2 (reg)", "0101 1101 0010 0---")
INST(HSETP2_cbuf, "HSETP2 (cbuf)", "0111 111- 1--- ----")
INST(HSETP2_imm, "HSETP2 (imm)", "0111 111- 0--- ----")
INST(I2F_reg, "I2F (reg)", "0101 1100 1011 1---")
INST(I2F_cbuf, "I2F (cbuf)", "0100 1100 1011 1---")
INST(I2F_imm, "I2F (imm)", "0011 100- 1011 1---")
INST(I2I_reg, "I2I (reg)", "0101 1100 1110 0---")
INST(I2I_cbuf, "I2I (cbuf)", "0100 1100 1110 0---")
INST(I2I_imm, "I2I (imm)", "0011 100- 1110 0---")
INST(IADD_reg, "IADD (reg)", "0101 1100 0001 0---")
INST(IADD_cbuf, "IADD (cbuf)", "0100 1100 0001 0---")
INST(IADD_imm, "IADD (imm)", "0011 100- 0001 0---")
INST(IADD3_reg, "IADD3 (reg)", "0101 1100 1100 ----")
INST(IADD3_cbuf, "IADD3 (cbuf)", "0100 1100 1100 ----")
INST(IADD3_imm, "IADD3 (imm)", "0011 100- 1100 ----")
INST(IADD32I, "IADD32I", "0001 110- ---- ----")
INST(ICMP_reg, "ICMP (reg)", "0101 1011 0100 ----")
INST(ICMP_rc, "ICMP (rc)", "0101 0011 0100 ----")
INST(IADD3_reg, "IADD3 (reg)", "0101 1100 1100 ----")
INST(IADD_imm, "IADD (imm)", "0011 100- 0001 0---")
INST(ICMP_cr, "ICMP (cr)", "0100 1011 0100 ----")
INST(ICMP_imm, "ICMP (imm)", "0011 011- 0100 ----")
INST(ICMP_rc, "ICMP (rc)", "0101 0011 0100 ----")
INST(ICMP_reg, "ICMP (reg)", "0101 1011 0100 ----")
INST(IDE, "IDE", "1110 0011 1001 ----")
INST(IDP_reg, "IDP (reg)", "0101 0011 1111 1---")
INST(IDP_imm, "IDP (imm)", "0101 0011 1101 1---")
INST(IMAD_reg, "IMAD (reg)", "0101 1010 0--- ----")
INST(IMAD_rc, "IMAD (rc)", "0101 0010 0--- ----")
INST(IMAD_cr, "IMAD (cr)", "0100 1010 0--- ----")
INST(IMAD_imm, "IMAD (imm)", "0011 010- 0--- ----")
INST(IMAD32I, "IMAD32I", "1000 00-- ---- ----")
INST(IMADSP_reg, "IMADSP (reg)", "0101 1010 1--- ----")
INST(IMADSP_rc, "IMADSP (rc)", "0101 0010 1--- ----")
INST(IMADSP_cr, "IMADSP (cr)", "0100 1010 1--- ----")
INST(IMADSP_imm, "IMADSP (imm)", "0011 010- 1--- ----")
INST(IMNMX_reg, "IMNMX (reg)", "0101 1100 0010 0---")
INST(IMNMX_cbuf, "IMNMX (cbuf)", "0100 1100 0010 0---")
INST(IMNMX_imm, "IMNMX (imm)", "0011 100- 0010 0---")
INST(IMUL_reg, "IMUL (reg)", "0101 1100 0011 1---")
INST(IMUL_cbuf, "IMUL (cbuf)", "0100 1100 0011 1---")
INST(IMUL_imm, "IMUL (imm)", "0011 100- 0011 1---")
INST(IMUL32I, "IMUL32I", "0001 1111 ---- ----")
INST(IPA, "IPA", "1110 0000 ---- ----")
INST(ISBERD, "ISBERD", "1110 1111 1101 0---")
INST(ISCADD_reg, "ISCADD (reg)", "0101 1100 0001 1---")
INST(ISCADD_cbuf, "ISCADD (cbuf)", "0100 1100 0001 1---")
INST(ISCADD_imm, "ISCADD (imm)", "0011 100- 0001 1---")
INST(ISCADD32I, "ISCADD32I", "0001 01-- ---- ----")
INST(ISET_reg, "ISET (reg)", "0101 1011 0101 ----")
INST(ISET_cbuf, "ISET (cbuf)", "0100 1011 0101 ----")
INST(ISET_imm, "ISET (imm)", "0011 011- 0101 ----")
INST(ISETP_reg, "ISETP (reg)", "0101 1011 0110 ----")
INST(ISETP_cbuf, "ISETP (cbuf)", "0100 1011 0110 ----")
INST(ISETP_imm, "ISETP (imm)", "0011 011- 0110 ----")
INST(ISETP_reg, "ISETP (reg)", "0101 1011 0110 ----")
INST(ISET_cbuf, "ISET (cbuf)", "0100 1011 0101 ----")
INST(ISET_reg, "ISET (reg)", "0101 1011 0101 ----")
INST(JCAL, "JCAL", "1110 0010 0010 ----")
INST(JMP, "JMP", "1110 0010 0001 ----")
INST(JMX, "JMX", "1110 0010 0000 ----")
INST(KIL, "KIL", "1110 0011 0011 ----")
INST(LD, "LD", "100- ---- ---- ----")
INST(LDC, "LDC", "1110 1111 1001 0---")
INST(LDG, "LDG", "1110 1110 1101 0---")
INST(LDL, "LDL", "1110 1111 0100 0---")
INST(LDS, "LDS", "1110 1111 0100 1---")
INST(LEA_hi_reg, "LEA (hi reg)", "0101 1011 1101 1---")
INST(LEA_hi_cbuf, "LEA (hi cbuf)", "0001 10-- ---- ----")
INST(LEA_lo_reg, "LEA (lo reg)", "0101 1011 1101 0---")
INST(LEA_lo_cbuf, "LEA (lo cbuf)", "0100 1011 1101 ----")
INST(LEA_lo_imm, "LEA (lo imm)", "0011 011- 1101 0---")
INST(LEPC, "LEPC", "0101 0000 1101 0---")
INST(LONGJMP, "LONGJMP", "1110 0011 0001 ----")
INST(LOP_reg, "LOP (reg)", "0101 1100 0100 0---")
INST(LOP_cbuf, "LOP (cbuf)", "0100 1100 0100 0---")
INST(LOP_imm, "LOP (imm)", "0011 100- 0100 0---")
INST(LOP3_reg, "LOP3 (reg)", "0101 1011 1110 0---")
INST(LOP3_cbuf, "LOP3 (cbuf)", "0000 001- ---- ----")
INST(LOP3_imm, "LOP3 (imm)", "0011 11-- ---- ----")
INST(LOP32I, "LOP32I", "0000 01-- ---- ----")
INST(MEMBAR, "MEMBAR", "1110 1111 1001 1---")
INST(MOV_reg, "MOV (reg)", "0101 1100 1001 1---")
INST(MOV_cbuf, "MOV (cbuf)", "0100 1100 1001 1---")
INST(MOV_imm, "MOV (imm)", "0011 100- 1001 1---")
INST(MOV32I, "MOV32I", "0000 0001 0000 ----")
INST(MUFU, "MUFU", "0101 0000 1000 0---")
INST(NOP, "NOP", "0101 0000 1011 0---")
INST(OUT_reg, "OUT (reg)", "1111 1011 1110 0---")
INST(OUT_cbuf, "OUT (cbuf)", "1110 1011 1110 0---")
INST(MOV_imm, "MOV (imm)", "0011 100- 1001 1---")
INST(OUT_imm, "OUT (imm)", "1111 011- 1110 0---")
INST(P2R_reg, "P2R (reg)", "0101 1100 1110 1---")
INST(P2R_cbuf, "P2R (cbuf)", "0100 1100 1110 1---")
INST(P2R_imm, "P2R (imm)", "0011 1000 1110 1---")
INST(PBK, "PBK", "1110 0010 1010 ----")
INST(PCNT, "PCNT", "1110 0010 1011 ----")
INST(PEXIT, "PEXIT", "1110 0010 0011 ----")
INST(PIXLD, "PIXLD", "1110 1111 1110 1---")
INST(PLONGJMP, "PLONGJMP", "1110 0010 1000 ----")
INST(POPC_reg, "POPC (reg)", "0101 1100 0000 1---")
INST(POPC_cbuf, "POPC (cbuf)", "0100 1100 0000 1---")
INST(POPC_imm, "POPC (imm)", "0011 100- 0000 1---")
INST(PRET, "PRET", "1110 0010 0111 ----")
INST(PRMT_reg, "PRMT (reg)", "0101 1011 1100 ----")
INST(PRMT_rc, "PRMT (rc)", "0101 0011 1100 ----")
INST(PRMT_cr, "PRMT (cr)", "0100 1011 1100 ----")
INST(PRMT_imm, "PRMT (imm)", "0011 011- 1100 ----")
INST(PSET, "PSET", "0101 0000 1000 1---")
INST(PSETP, "PSETP", "0101 0000 1001 0---")
INST(R2B, "R2B", "1111 0000 1100 0---")
INST(R2P_reg, "R2P (reg)", "0101 1100 1111 0---")
INST(R2P_cbuf, "R2P (cbuf)", "0100 1100 1111 0---")
INST(PRMT_rc, "PRMT (rc)", "0101 0011 1100 ----")
INST(PRMT_reg, "PRMT (reg)", "0101 1011 1100 ----")
INST(R2P_imm, "R2P (imm)", "0011 100- 1111 0---")
INST(RAM, "RAM", "1110 0011 1000 ----")
INST(RED, "RED", "1110 1011 1111 1---")
INST(RET, "RET", "1110 0011 0010 ----")
INST(RRO_reg, "RRO (reg)", "0101 1100 1001 0---")
INST(RRO_cbuf, "RRO (cbuf)", "0100 1100 1001 0---")
INST(RRO_imm, "RRO (imm)", "0011 100- 1001 0---")
INST(RTT, "RTT", "1110 0011 0110 ----")
INST(S2R, "S2R", "1111 0000 1100 1---")
INST(SAM, "SAM", "1110 0011 0111 ----")
INST(SEL_reg, "SEL (reg)", "0101 1100 1010 0---")
INST(SEL_cbuf, "SEL (cbuf)", "0100 1100 1010 0---")
INST(SEL_imm, "SEL (imm)", "0011 100- 1010 0---")
INST(SETCRSPTR, "SETCRSPTR", "1110 0010 1110 ----")
INST(SETLMEMBASE, "SETLMEMBASE", "1110 0010 1111 ----")
INST(SHF_l_reg, "SHF (l reg)", "0101 1011 1111 1---")
INST(SHF_l_imm, "SHF (l imm)", "0011 011- 1111 1---")
INST(SHF_r_reg, "SHF (r reg)", "0101 1100 1111 1---")
INST(SHF_r_imm, "SHF (r imm)", "0011 100- 1111 1---")
INST(SHFL, "SHFL", "1110 1111 0001 0---")
INST(SHL_reg, "SHL (reg)", "0101 1100 0100 1---")
INST(SHL_cbuf, "SHL (cbuf)", "0100 1100 0100 1---")
INST(SHL_imm, "SHL (imm)", "0011 100- 0100 1---")
INST(SHR_reg, "SHR (reg)", "0101 1100 0010 1---")
INST(SHR_cbuf, "SHR (cbuf)", "0100 1100 0010 1---")
INST(SHR_imm, "SHR (imm)", "0011 100- 0010 1---")
INST(SSY, "SSY", "1110 0010 1001 ----")
INST(ST, "ST", "101- ---- ---- ----")
INST(STG, "STG", "1110 1110 1101 1---")
INST(STL, "STL", "1110 1111 0101 0---")
INST(STP, "STP", "1110 1110 1010 0---")
INST(STS, "STS", "1110 1111 0101 1---")
INST(SUATOM, "SUATOM", "1110 1010 0--- ----")
INST(SUATOM_cas, "SUATOM_cas", "1110 1010 1--- ----")
INST(CCTL, "CCTL", "1110 1111 011- ----")
INST(CCTLL, "CCTLL", "1110 1111 100- ----")
INST(DFMA_imm, "DFMA (imm)", "0011 011- 0111 ----")
INST(DSETP_imm, "DSETP (imm)", "0011 011- 1000 ----")
INST(FCMP_imm, "FCMP (imm)", "0011 011- 1010 ----")
INST(FSETP_imm, "FSETP (imm)", "0011 011- 1011 ----")
INST(IADD3_imm, "IADD3 (imm)", "0011 100- 1100 ----")
INST(ICMP_imm, "ICMP (imm)", "0011 011- 0100 ----")
INST(ISETP_imm, "ISETP (imm)", "0011 011- 0110 ----")
INST(ISET_imm, "ISET (imm)", "0011 011- 0101 ----")
INST(PRMT_imm, "PRMT (imm)", "0011 011- 1100 ----")
INST(SULD, "SULD", "1110 1011 000- ----")
INST(SURED, "SURED", "1110 1011 010- ----")
INST(SUST, "SUST", "1110 1011 001- ----")
INST(SYNC, "SYNC", "1111 0000 1111 1---")
INST(TEX, "TEX", "1100 0--- ---- ----")
INST(TEX_b, "TEX (b)", "1101 1110 10-- ----")
INST(TEXS, "TEXS", "1101 -00- ---- ----")
INST(TLD, "TLD", "1101 1100 ---- ----")
INST(TLD_b, "TLD (b)", "1101 1101 ---- ----")
INST(TLD4, "TLD4", "1100 10-- ---- ----")
INST(TLD4_b, "TLD4 (b)", "1101 1110 11-- ----")
INST(TLD4S, "TLD4S", "1101 1111 -0-- ----")
INST(TLDS, "TLDS", "1101 -01- ---- ----")
INST(TMML, "TMML", "1101 1111 0101 1---")
INST(TMML_b, "TMML (b)", "1101 1111 0110 0---")
INST(TXA, "TXA", "1101 1111 0100 0---")
INST(TXD, "TXD", "1101 1110 00-- ----")
INST(TXD_b, "TXD (b)", "1101 1110 01-- ----")
INST(TXQ, "TXQ", "1101 1111 0100 1---")
INST(TXQ_b, "TXQ (b)", "1101 1111 0101 0---")
INST(VABSDIFF, "VABSDIFF", "0101 0100 ---- ----")
INST(XMAD_reg, "XMAD (reg)", "0101 1011 00-- ----")
INST(DSET_cbuf, "DSET (cbuf)", "0100 1001 0--- ----")
INST(DSET_reg, "DSET (reg)", "0101 1001 0--- ----")
INST(FFMA_cr, "FFMA (cr)", "0100 1001 1--- ----")
INST(FFMA_rc, "FFMA (rc)", "0101 0001 1--- ----")
INST(FFMA_reg, "FFMA (reg)", "0101 1001 1--- ----")
INST(IMADSP_cr, "IMADSP (cr)", "0100 1010 1--- ----")
INST(IMADSP_rc, "IMADSP (rc)", "0101 0010 1--- ----")
INST(IMADSP_reg, "IMADSP (reg)", "0101 1010 1--- ----")
INST(IMAD_cr, "IMAD (cr)", "0100 1010 0--- ----")
INST(IMAD_rc, "IMAD (rc)", "0101 0010 0--- ----")
INST(IMAD_reg, "IMAD (reg)", "0101 1010 0--- ----")
INST(SUATOM, "SUATOM", "1110 1010 0--- ----")
INST(SUATOM_cas, "SUATOM_cas", "1110 1010 1--- ----")
INST(TLD4S, "TLD4S", "1101 1111 -0-- ----")
INST(VABSDIFF4, "VABSDIFF4", "0101 0000 0--- ----")
INST(VADD, "VADD", "0010 00-- ---- ----")
INST(XMAD_imm, "XMAD (imm)", "0011 011- 00-- ----")
INST(XMAD_rc, "XMAD (rc)", "0101 0001 0--- ----")
INST(ATOM, "ATOM", "1110 1101 ---- ----")
INST(ATOMS, "ATOMS", "1110 1100 ---- ----")
INST(ATOMS_cas, "ATOMS (cas)", "1110 1110 ---- ----")
INST(DSET_imm, "DSET (imm)", "0011 001- 0--- ----")
INST(FFMA_imm, "FFMA (imm)", "0011 001- 1--- ----")
INST(FMUL32I, "FMUL32I", "0001 1110 ---- ----")
INST(FSET_cbuf, "FSET (cbuf)", "0100 1000 ---- ----")
INST(FSET_reg, "FSET (reg)", "0101 1000 ---- ----")
INST(HADD2_cbuf, "HADD2 (cbuf)", "0111 101- 1--- ----")
INST(HADD2_imm, "HADD2 (imm)", "0111 101- 0--- ----")
INST(HMUL2_cbuf, "HMUL2 (cbuf)", "0111 100- 1--- ----")
INST(HMUL2_imm, "HMUL2 (imm)", "0111 100- 0--- ----")
INST(HSET2_cbuf, "HSET2 (cbuf)", "0111 110- 1--- ----")
INST(HSET2_imm, "HSET2 (imm)", "0111 110- 0--- ----")
INST(HSETP2_cbuf, "HSETP2 (cbuf)", "0111 111- 1--- ----")
INST(HSETP2_imm, "HSETP2 (imm)", "0111 111- 0--- ----")
INST(IMADSP_imm, "IMADSP (imm)", "0011 010- 1--- ----")
INST(IMAD_imm, "IMAD (imm)", "0011 010- 0--- ----")
INST(IMUL32I, "IMUL32I", "0001 1111 ---- ----")
INST(IPA, "IPA", "1110 0000 ---- ----")
INST(TLD, "TLD", "1101 1100 ---- ----")
INST(TLD_b, "TLD (b)", "1101 1101 ---- ----")
INST(VABSDIFF, "VABSDIFF", "0101 0100 ---- ----")
INST(VMAD, "VMAD", "0101 1111 ---- ----")
INST(VMNMX, "VMNMX", "0011 101- ---- ----")
INST(VOTE, "VOTE", "0101 0000 1101 1---")
INST(VOTE_vtg, "VOTE (vtg)", "0101 0000 1110 0---")
INST(VSET, "VSET", "0100 000- ---- ----")
INST(VSETP, "VSETP", "0101 0000 1111 0---")
INST(VSHL, "VSHL", "0101 0111 ---- ----")
INST(VSHR, "VSHR", "0101 0110 ---- ----")
INST(XMAD_reg, "XMAD (reg)", "0101 1011 00-- ----")
INST(XMAD_rc, "XMAD (rc)", "0101 0001 0--- ----")
INST(FSET_imm, "FSET (imm)", "0011 000- ---- ----")
INST(HADD2_32I, "HADD2_32I", "0010 110- ---- ----")
INST(HFMA2_32I, "HFMA2_32I", "0010 100- ---- ----")
INST(HMUL2_32I, "HMUL2_32I", "0010 101- ---- ----")
INST(IADD32I, "IADD32I", "0001 110- ---- ----")
INST(LOP3_cbuf, "LOP3 (cbuf)", "0000 001- ---- ----")
INST(VMNMX, "VMNMX", "0011 101- ---- ----")
INST(VSET, "VSET", "0100 000- ---- ----")
INST(XMAD_cr, "XMAD (cr)", "0100 111- ---- ----")
INST(XMAD_imm, "XMAD (imm)", "0011 011- 00-- ----")
// Removed due to its weird formatting making fast tables larger
// INST(CCTLT, "CCTLT", "1110 1011 1111 0--0")
INST(FADD32I, "FADD32I", "0000 10-- ---- ----")
INST(FFMA32I, "FFMA32I", "0000 11-- ---- ----")
INST(HFMA2_cr, "HFMA2 (cr)", "0111 0--- 1--- ----")
INST(HFMA2_imm, "HFMA2 (imm)", "0111 0--- 0--- ----")
INST(HFMA2_rc, "HFMA2 (rc)", "0110 0--- 1--- ----")
INST(IMAD32I, "IMAD32I", "1000 00-- ---- ----")
INST(ISCADD32I, "ISCADD32I", "0001 01-- ---- ----")
INST(LEA_hi_cbuf, "LEA (hi cbuf)", "0001 10-- ---- ----")
INST(LOP32I, "LOP32I", "0000 01-- ---- ----")
INST(LOP3_imm, "LOP3 (imm)", "0011 11-- ---- ----")
INST(TEXS, "TEXS", "1101 -00- ---- ----")
INST(TLD4, "TLD4", "1100 10-- ---- ----")
INST(TLDS, "TLDS", "1101 -01- ---- ----")
INST(VADD, "VADD", "0010 00-- ---- ----")
INST(TEX, "TEX", "1100 0--- ---- ----")
INST(LD, "LD", "100- ---- ---- ----")
INST(ST, "ST", "101- ---- ---- ----")

1
src/shader_recompiler/frontend/maxwell/translate/impl/impl.h
View File

@ -86,6 +86,7 @@ public:
void CAL();
void CCTL(u64 insn);
void CCTLL(u64 insn);
void CCTLT(u64 insn);
void CONT(u64 insn);
void CS2R(u64 insn);
void CSET(u64 insn);

7
src/shader_recompiler/frontend/maxwell/translate/impl/not_implemented.cpp
View File

@ -1,3 +1,6 @@
// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project
// SPDX-License-Identifier: GPL-3.0-or-later
// SPDX-FileCopyrightText: Copyright 2021 yuzu Emulator Project
// SPDX-License-Identifier: GPL-2.0-or-later
@ -48,6 +51,10 @@ void TranslatorVisitor::CCTLL(u64) {
ThrowNotImplemented(Opcode::CCTLL);
}
void TranslatorVisitor::CCTLT(u64) {
ThrowNotImplemented(Opcode::CCTLT);
}
void TranslatorVisitor::CONT(u64) {
ThrowNotImplemented(Opcode::CONT);
}