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Partial revert "[shared_recompiler/maxwell] fix SURED() wrong encodings (#2983)" (#3099) 

Signed-off-by: Caio Oliveira <caiooliveirafarias0@gmail.com>
Reviewed-on: https://git.eden-emu.dev/eden-emu/eden/pulls/3099
Reviewed-by: Lizzie <lizzie@eden-emu.dev>
Reviewed-by: MaranBr <maranbr@eden-emu.dev>
Co-authored-by: Caio Oliveira <caiooliveirafarias0@gmail.com>
Co-committed-by: Caio Oliveira <caiooliveirafarias0@gmail.com>
This commit is contained in:
Caio Oliveira 2025-11-26 22:57:00 +01:00 committed by crueter
parent 41af6ea645
commit 9e610ea098
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1 changed files with 4 additions and 3 deletions
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7
src/shader_recompiler/frontend/maxwell/translate/impl/surface_atomic_operations.cpp
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@ -195,9 +195,9 @@ void TranslatorVisitor::SUATOM(u64 insn) {
void TranslatorVisitor::SURED(u64 insn) {
// TODO: confirm offsets
// SURED unlike SUATOM does NOT have a binded register
union {
u64 raw;
BitField<51, 1, u64> is_bound;
BitField<24, 3, AtomicOp> op; //OK - 24 (SURedOp)
BitField<33, 3, Type> type; //OK? - 33 (Dim)
BitField<20, 3, Size> size; //?
@ -205,10 +205,11 @@ void TranslatorVisitor::SURED(u64 insn) {
BitField<0, 8, IR::Reg> operand_reg; //RA?
BitField<8, 8, IR::Reg> coord_reg; //RB?
BitField<36, 13, u64> bound_offset; //OK 33 (TidB)
BitField<39, 8, IR::Reg> bindless_reg; // !is_bound
} const sured{insn};
ImageAtomOp(*this, IR::Reg::RZ, sured.operand_reg, sured.coord_reg, std::nullopt,
ImageAtomOp(*this, IR::Reg::RZ, sured.operand_reg, sured.coord_reg, sured.bindless_reg,
sured.op, sured.clamp, sured.size, sured.type, sured.bound_offset,
false, false);
sured.is_bound == 0, false);
}
} // namespace Shader::Maxwell